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NXP Semiconductors /LPC43xx /CCU2 /CLK_APB0_SSP0_CFG

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Interpret as CLK_APB0_SSP0_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)RUN 0 (DISABLED_)AUTO 0 (DISABLED)WAKEUP 0RESERVED

AUTO=DISABLED_, WAKEUP=DISABLED, RUN=DISABLED

Description

CLK_APB0_SSP0 clock configuration register

Fields

RUN

Run enable

0 (DISABLED): Clock is disabled.

1 (ENABLED): Clock is enabled.
AUTO

Auto (AHB disable mechanism) enable

0 (DISABLED_): Auto is disabled.

1 (ENABLED): Auto is enabled.
WAKEUP

Wake-up mechanism enable

0 (DISABLED): Wake-up is disabled.

1 (ENABLED): Wake-up is enabled.
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data